In the prior art, there is the wiring substrate (semiconductor package) for mounting the semiconductor chip thereon. The wiring substrate is constructed such that the build-up wiring is formed on both surface sides of the core substrate.
In Patent Literature 1 (Japanese Laid-Patent Publication No. 2008-112765), it is set forth that mechanical strength of the portions located at four corners of the substrate should be improved by replacing a plurality of metal lands arranged at four corners of the wiring substrate conventionally with one integrated metal land.
Also, in Patent Literature 2 (Japanese Laid-Patent Publication No. 2002-329802), it is set forth that, in the semiconductor package, the pad to which each external connection terminal (pin) is connected is divided into a plurality of pads, and then the wiring connected to another pad is arranged between the pads which are arranged to be divided.
As explained in the column of the related art described later, in the wiring substrate on which the semiconductor chip is mounted, there is such a tendency that a design rule applied to the wiring layer located under the upper surface layer is reduced to the utmost extent.
In the wiring substrate, one via conductor connected to a main portion of the connection pad is arranged under each connection pad, and the via conductor is arranged on the via pad, which is arranged with the equal area to the connection pad, of the lower wiring layer, thus the interlayer connection is provided.
In a situation that a further increase in a wiring density of the lower wiring layers (an increase in the number of wirings) is demanded, a narrower pitch of the lower wiring layers can be implemented by introducing the high-level photolithography technology. In this case, a huge capital investment and a change in process are needed, and therefore such introduction cannot be easily applied in actuality. As a result, a minimum design rule is decided depending on whether or not how many wirings can be arranged between the via pads of the lower wiring layer by the existing photolithography technology.
Also, in the related art, the via pads of the lower wiring layer are arranged in a size which corresponds to the connection pad. Therefore, the presence of the via pads inhibits an increase in a wiring density of the lower wiring layers.